SMT: Esd Control And Handling Procedure

11 Handling and ESD control

1. 1. Electrostatic discharge
2. 2. ESD and EOS (Electrical Overstress)
3. 3. Surface resistivity
4. 4. Human body model
5. 5. Requirements of static-free work station
6. 6. Places where ESD control is required
7. 7. Summary

1. Electrostatic discharge

Electrostatic discharge is defined as the transfer of electrostatic charge between bodies at different electrostatic potentials caused by direct contact or induced by an electrostatic field.

The usual ESD consists of the release of stored charge from a capacitive item, the capacitive item in the most fundamental form is the human body. Other typical charge storing bodies include chassis, clothing, chairs etc. Most ESD failures occur below the human sense of feeling to static discharge which begins at about 4000 V. However, majority of integrated circuits and many discrete parts fail at thresholds below 4000V. The sensation of feeling from static discharge is rare occurrence except under extremely dry atmospheric conditions.

Typical susceptibility levels:

2. ESD and EOS (Electrical Overstress):

Electrical overstress (EOS) failure other than ESD is usually of longer time duration, generally greater than 50 ms. Typical EOS sources are 230 VAC, 50 Hz, accidental short to a dc or ac potential exceeding the gate-oxide breakdown or system transients of varying durations. In these cases the heating is normally sustained longer than during the typical ESD exposure, thus resulting in more extensive damage. Generally, EOS transients are of longer duration than ESD transients. In addition EOS- caused failures can be of either forward or reverse bias. Forward bias EOS is typically evidenced by resultant damage of high currents such as melting and / vaporization of intra-connects. For example, a TTL input gate exposed to 14V for 200 ms with a peak current of 500 mA resulting in the high current melting of intraconnects.

The most prevalent junction damage from ESD occurs in the reverse biased condition and is evidenced by a degraded I-V characteristic. Degradation can be from a nearly negligible shift of the curve to a short circuit. Physical damage is invisible upon microscopic examination of the chip surface, except in most severe cases.

3. Surface resistivity:

For a surface, the resistance decreases in proportion to the width, W, and increases proportionately with length, l.

Resistivity, R is given by

R= k l /W

Where k is a proportionality constant.
In case of a square, where l =W, the equation reduces to

R=k

As can be seen from the equation, if l=W, the size of l and W does not matter, so the size of the square is immaterial. In other words,

rs= surface resistivity =k = resistance when l = W

The terms for categorization of materials by surface resistivity are currently defined as follows:

Conductive:<= 10 5per square
Static dissipative: 10 5 to 10 9W
Antistatic: 10 9 to 10 14W per square
Insulative: > 10 14 W per square

However, the above are only indicative and the limits may be tailored to individual requirements if necessary.

Effect of humidity:

Higher humidity will increase the moisture content of materials to varying degrees depending upon the material. This increased moisture content will reduce the resistivity.